Normotensive offspring with non-dipper hypertensive parents have abnormal sleep pattern.

The objective of this study was to determine whether abnormal microstructure of sleep in non-dipper hypertensive patients was present in their offspring. Subjects included 11 normotensive offspring of non-dipper hypertensive parents (FH + ND), 6 of dipper hypertensive parents (FH + D) and 5 of normotensive parents (Controls). We measured blood pressure beat-to-beat by Finapres and all stages of sleep by polysomnographically recording simultaneously during spontaneous nocturnal sleep. We analysed blood pressure pattern for 4-min long random periods while the subjects were awake and during all stages of sleep; sleep efficiency (SE), sleep latency (SL), delta-sleep latency (delta-SL), REM sleep latency (REM-SL), Stage 1, Stage 2, Stage 3, Stage 4 and REM duration and percentage values, and microstructural aspects of sleep (arousal and microarousal temporization and features). FH + D and controls showed a fall in blood pressure greater than 10% in all stages of NREM sleep and in the FH + ND blood pressure fall in less than 10% of waking values in all NREM stages. REM sleep and heart rate were similar in the three groups during all stages of sleep. FH + ND showed the same number of arousals but more microarousals than FH + D and controls (p < 0.0001). Microarousals induced several stage shifts through lighter sleep. For this reason, FH + ND spent more time in stage 2 than FH + D and controls. In conclusion, offspring of non-dipper hypertension parents showed a greater number of microarousals than the other two groups

Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs

NTRODUCTION \u2015 In the past decade the Tunnel Field Effect Transistor (TFET) relying on band-to-band tunneling (BTBT) has emerged as one of the most promising small slope FETs able to achieve a subthreshold swing (SS) below the room temperature 60 mV/dec limit of conventional MOSFET [1]. Many simulation studies attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (VDD < 0.4 V) in both analog [2-3] and digital [4-7] applications. However, only basic digital and analog circuits have been fabricated up to date, such as current mirrors [8] and inverter gates [9]. As for semiconductor materials, III-V hetero-structure TFETs may be able to achieve a sub-thermal SS in a wide current range and, at the same time, very competitive on currents [1], as demonstrated by a recently fabricated vertical InAs/GaAsSb/GaSb nanowire n-type TFETs [10]. The aim of this work is to benchmark a complementary III-V TFET technology platform against the mainstream FinFET reference, by considering basic building blocks of digital and analog applications. To this purpose, we selected a complementary III-V TFET technology platform designed and optimized using full quantum simulations in [11], where n- and p-type TFET pairs are realized in the same InAs/AlGaSb material system. The use of such devices allowed us to remove the excessively optimistic assumption of perfectly symmetric n- and p-type TFETs, very frequently embraced in previous simulation studies (e.g. in [2, 7]). We present circuit-level simulations performed on current mirrors and inverter-based logic blocks, which are identified as basic topologies representative of the analog and digital design realms, respectively. Similar benchmarking results for the same technology platforms have been obtained by focusing the comparison on more complicated circuit blocks [3], [5] and [6]

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n-and p-Type I-V exts , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing

Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memor

Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation

Abstract In this work three-dimensional (3-D) numerical simulations, validated by the experimental measurements of a reference cell, have been performed to optimize the rear contact geometry of a PERC-type solar cell, featuring a high sheet resistance (140 Ω/sq) phosphorus-doped emitter and a front-side metallization with narrow and highly-conductive electro-plated copper lines (40 μm wide) on lowly resistive Ti contacts. The simulation results show that an optimization of the rear point contact design potentially leads to an efficiency improvement of 0.68%abs compared to the reference cell